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논문 기본 정보

자료유형
학술저널
저자정보
Yunlu Li (Northeastern University) Dazhi Wang (Northeastern University) Wei Han (Inner Mongolia University for the Nationalities) Zhenao Sun (Northeastern University) Tianqing Yuan (Northeastern University)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.17 No.3
발행연도
2017.5
수록면
704 - 715 (12page)

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초록· 키워드

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For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.

목차

Abstract
I. INTRODUCTION
II. HYBRID FILTERING STAGE IN THE PROPOSED PLL
III. THE PROPOSED PLL AND PARAMETER DESIGN GUIDELINES
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES

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