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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.3
- 발행연도
- 2015.6
- 수록면
- 342 - 348 (7page)
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초록· 키워드
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This paper presents a 1.9-GHz digital ΔΣ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CIRCUIT DESCRIPTION
Ⅲ. OPTIMUM NUMBER OF TAPS
Ⅳ. MEASUREMENTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (11)
참고문헌 신청
[학술지(정기간행물)] - D.-W. Jee / 2011 / A 0.1-fref BW 1 GHz fractional-N PLL with FIRembedded phase-interpolator-based noise filtering / ISSCC Dig. Tech. Papers : 94 ~ 95
[학술지(정기간행물)] - X. Yu / 2009 / An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators / IEEE J. Solid- State Circuits 44 (9) : 2426 ~ 2436
[학술지(정기간행물)] - Anil Kavala / 2014 / A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 14 (4) : 484 ~ 494
[학술지(정기간행물)] - D.-W. Jee / 2012 / A 2GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC / IEEE J. Solid- State Circuits 47 (4) : 875 ~ 883
[학술지(정기간행물)] - X. Yu / 2009 / A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications / IEEE J. Solid-State Circuits 44 (8) : 2193 ~ 2200
[학술지(정기간행물)] - X. Yu / 2009 / An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators / IEEE J. Solid- State Circuits 44 (9) : 2426 ~ 2436
[학술지(정기간행물)] - Anil Kavala / 2014 / A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 14 (4) : 484 ~ 494
[학술지(정기간행물)] - D.-W. Jee / 2012 / A 2GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC / IEEE J. Solid- State Circuits 47 (4) : 875 ~ 883
[학술지(정기간행물)] - X. Yu / 2009 / A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications / IEEE J. Solid-State Circuits 44 (8) : 2193 ~ 2200
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