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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.25 No.1
- 발행연도
- 2025.2
- 수록면
- 14 - 20 (7page)
- DOI
- 10.5573/JSTS.2025.25.1.14
이용수
초록· 키워드
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This paper presents a second-order modified feed-forward (FF) delta-sigma modulator for battery management system DC measurement. The proposed ADC employs a modified 3-bit feedback digital-to-analog converter (DAC) with the data weight averaging (DWA) technique to improve the capacitance matching. The modified 3-bit DAC reduces the logic complexity of the DWA by simplifying the switching network of unit capacitors. Additionally, the proposed ADC adopts capacitor swapping technique between the input and reference sampling capacitors to minimize its gain error. To further improve the performance of the proposed ADC, system-level lowfrequency chopping (CHL) and correlated double sampling (CDS) are employed to mitigate offset and flicker noise. The prototype ADC is fabricated in a 180 nm CMOS process, and the core area is 0.53 mm². It consumes 9.48 μW from a 1.8 V supply voltage at an operating clock frequency of 19.2 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 102.4 dB, a resolution of 7 μVrms, and an offset of 6.86 μV, resulting in a Schreier figure-of-merit (FoM) of 165.3 dB.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED ARCHITECTURE
Ⅲ. CIRCUIT IMPLEMENTATION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSION
REFERENCES
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